1. Field of the Invention
The present invention relates generally to digital-to-analog converters (DACs) and more particularly to precision DACs.
2. Description of the Related Art
Digital-to-analog converters convert a digital input signal into an analog output signal. This process is exemplified in the graph 20 of FIG. 1 which illustrates output signals for each digital code of a 3-bit digital input signal. The analog response signals are shown as vertical analog columns whose heights represent portions of the converter's full scale output. For example, the digital input code 011 is associated with a vertical column 22 whose analog amplitude is 3/8 of the DAC's full scale output.
If a DAC has an absence of conversion error, all of the vertical columns of the graph 20 will have exactly the correct height so that their upper tips fall on a line 24 that is the locus of an error-free output because it connects the zero and full scale analog points. The line 24 is thus the locus of ideal DAC conversion.
Practical DACs, however, do generate errors in their converted analog output. The 000 vertical column of FIG. 1, for example, may have a non-zero height and the upper tips of the vertical analog columns may then lie on a locus line 26 that is spaced from the error-free locus line 24. The locus line 26 exemplifies an offset error. In contrast, a DAC gain error is exemplified by a condition in which the tips of the vertical columns lie on a locus line 28 that begins at zero but has a slope which causes it to have a full scale error.
In many DAC applications, offset and gain errors can be compensated. A more critical error is nonlinearity which is typically defined in terms of integral nonlinearity and differential nonlinearity. Integral nonlinearity is a measure of the maximum deviation from the error-free line 24 and is exemplified by the exemplary locus envelopes 30 in FIG. 1.
Differential linearity refers to the analog linearity exhibited by adjacent digital input codes. Full scale analog output divided by the number of bits yields the analog measure of one least-significant bit (LSB) as shown in FIG. 1. If first and second adjacent digital bits have plus and minus errors of 1/2+L LSB, then the analog output signal does not change between these digital codes. If the error is any greater between these adjacent digital bits, the analog signal declines as the second bit succeeds the first bit. The conversion is then said to be non-monotonic.
Although it is sufficient in many DAC applications to have a nonlinearity that does not exceed 1/2+L LSB, other applications require precision DACs in which nonlinearity is substantially reduced from 1/2+L LSB. An exemplary application is that of a subranging analog-to-digital converter (ADC) system in which conversion to a coarse set of digital bits is achieved in an initial ADC stage and an analog residue is formed and "pipelined" to subsequent ADC stages for further conversion.
In particular, the initial ADC converts an analog input signal into an initial set of digital bits. In response to this initial set, an initial DAC generates a converted analog signal which is subtracted from the input analog signal to form an analog residue signal which is then passed (pipelined) to a subsequent ADC.
If the subsequent ADC is not the final ADC, the foregoing process is repeated. That is, a subsequent DAC generates another converted analog signal which is again subtracted from the analog signal to form another analog residue signal which is pipelined to the following stage. The final ADC converts its respective residue signal into a final set of digital bits.
The conversion into the final set of digital bits cannot be more linear than the preceding conversion processes. If it is desired, for example, to realize a 12-bit subranging ADC with initial, subsequent and final 4-bit conversion stages, the initial 4-bit DAC must have 12-bit linearity and the subsequent 4-bit DAC must have 8-bit linearity.
Processing techniques and controls (e.g., statistical process matching) are typically employed to approach these precision DAC linearities but they generally must be supplemented by a one-time physical trim and/or a power-up calibration method. The time and cost associated with these latter processes would be substantially reduced with DACs that included a high-linearity programmable adjustment structure.